Full Adder in VHDL
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4
5 entity full_adder is
6 Port (
7 x,y,z: in std_logic;
8 C: out std_logic;
9 S: out std_logic
10 );
11 end full_adder;
12
13 architecture Boolean_expression of full_adder is
14
15 begin
16 S <= (x xor y xor z);
17 C <= (x and y) or (x and z) or (y and z);
18
19 end Boolean_expression;